The present invention relates to a test apparatus for a semiconductor device, and, more particularly, to a test apparatus equipped with a test circuit connected between a semiconductor device and an external test unit.
In case where a test for circuit functions or electric characteristics or the like is performed on a plurality of chips of semiconductor memory devices on a wafer, conventionally, a probe is made to contact a pad of each chip and is connected to a test apparatus via a connection cable. The test apparatus provides a predetermined test program to each chip and conducts individual function tests in accordance with the test program.
The probe test suffers a poor precision of signal waveforms to be supplied to the test apparatus and cannot sufficiently secure the reliability in an operational test on a semiconductor memory device which operates at a high speed.
As the operational speeds and the capacities of recent semiconductor memory devices are increased, there arises a problem such that the performance of an external test unit cannot follow up the characteristics of the semiconductor memory devices.
To supplement the performance of the external test unit, therefore, a test chip called Built Out Self Test (BOST) or a test circuit which is called Built In Self Test (BIST) and preformed in each chip is intervened between a wafer and the external test unit.
Japanese Laid-Open Patent Publication No. 2000-100880 or Japanese Laid-Open Patent Publication No. 9-49864 discloses a test apparatus which has a BOST or BIST provided between an external test unit and a circuit to be measured and performs an operational test.
However, all tests, such as a timing dependency test and a pattern dependency test, cannot be controlled by the BOST or BIST. In other words, there are test items that can be executed only in a low-speed operational test which is conducted by an external test unit. This makes it difficult to speed up an operational test on target devices on a wafer.